The present invention relates to a mask pattern design method and a photomask useful for designing a fine supplemental pattern.
In recent years, the semiconductor manufacturing techniques have extremely progressed, and semiconductor devices having a minimum processible size of 0.35 .mu.m have been manufactured in these days. This fine downsizing of devices is realized by rapid progress of a fine pattern forming technique called an optical lithography technique.
The optical lithography means a series of steps of: forming a mask from a design pattern of an LSI; irradiating light on the mask to expose a resist coated on the wafer in accordance with a pattern drawn on the mask by a projection optical system; and developing the resist based on the exposure distribution thereby to form a resist pattern on the wafer. By etching under layers with use of the resist pattern formed through the optical lithography steps, as a mask, an LSI pattern is formed on the wafer.
In a generation in which the pattern size was sufficiently large compared with the limit resolution of a projection optical system, the plan shape of the LSI pattern desired to be formed on the wafer was directly drawn as a design pattern. Further, a mask pattern having fidelity to the design pattern was prepared. The mask pattern thus obtained was transferred onto a wafer by a projection optical system, and under layers were etched. In this manner, a pattern substantially similar to the design pattern was formed on the wafer.
However, as the patterns have come to become finer and smaller, the pattern formed on the wafer differs from a design pattern due to influences from an eclipse iof diffracted light in a projection optical system (which will be hereinafter called an optical proximity effect), accompanying remarkable bad influences.
For example, in case of a gate pattern, the top end portion of the pattern becomes shorter than that of a design pattern (which will be hereinafter called "shortening"), or corner portions of a device region such as SDG or the like are rounded (which will be hereinafter called "rounding"). These shortening and rounding are factors which cause operation errors of transistors. Also, in case of forming a dense Line and Space (L/S) pattern, the line width of an isolated pattern existing in the same layer as the L/S pattern becomes thicker or narrower than that of a finished L/S pattern. This is a factor which deteriorates the operation characteristics of the device.
To eliminate these problems, there has been a proposal for a method in which correction is made by adding a fine small supplemental pattern to the portion of a pattern where the optical proximity effect appears, thereby to prepare a mask design plan different from a conventional design pattern, and a mask is prepared in accordance with the mask design plan. An example thereof is disclosed in Japanese Patent Application KOKAI Publication No. 6-242595. The method of transfer with use of a mask prepared by adding a fine small supplemental pattern to a design pattern is effective for forming a pattern with fidelity to the design pattern on a wafer.
However, the size of this supplement pattern is generally very small. More specifically, the dimensions of this supplemental pattern, as formed on a a wafer, are in the several-ten nm range. Consequently, errors in mask dimensions or rounding at corner portions, which are caused by mask drawing process, greatly influence the finished dimensions after transfer. Therefore, it is difficult to obtain an optical proximity effect stably. Also, improvements in precision of the mask drawing process require techniques which further require much labor.
Thus, in a conventional method, finished dimensions of a supplemental pattern vary due to the mask drawing process. As a result of this, it is difficult to stably attain a desired correction effect in a pattern after transfer.